| [1613] | 1 | #include "lolevel.h" |
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| 2 | #include "platform.h" |
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| 3 | #include "core.h" |
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| 4 | #include "dryos31.h" |
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| 5 | |
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| 6 | #define offsetof(TYPE, MEMBER) ((int) &((TYPE *)0)->MEMBER) |
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| 7 | |
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| 8 | const char * const new_sa = &_end; |
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| 9 | |
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| 10 | extern void task_CaptSeq(); |
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| 11 | extern void task_InitFileModules(); |
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| 12 | extern void task_MovieRecord(); |
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| 13 | extern void task_ExpDrv(); |
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| 14 | |
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| 15 | void taskHook(context_t **context) |
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| 16 | { |
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| 17 | task_t *tcb=(task_t*)((char*)context-offsetof(task_t, context)); |
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| 18 | |
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| 19 | // Replace firmware task addresses with ours |
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| 20 | if(tcb->entry == (void*)task_CaptSeq) tcb->entry = (void*)capt_seq_task; |
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| 21 | if(tcb->entry == (void*)task_InitFileModules) tcb->entry = (void*)init_file_modules_task; |
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| 22 | if(tcb->entry == (void*)task_MovieRecord) tcb->entry = (void*)movie_record_task; |
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| 23 | if(tcb->entry == (void*)task_ExpDrv) tcb->entry = (void*)exp_drv_task; |
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| 24 | } |
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| 25 | |
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| 26 | void CreateTask_spytask() { |
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| 27 | _CreateTask("SpyTask", 0x19, 0x2000, core_spytask, 0); |
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| 28 | }; |
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| 29 | |
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| 30 | |
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| 31 | |
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| 32 | |
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| 33 | void __attribute__((naked,noinline)) boot() { |
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| 34 | asm volatile ( |
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| 35 | // LED Test |
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| 36 | /* "LDR R1, =0xC0220088\n" // Green LED |
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| 37 | "MOV R0, #0x46\n" // Power on LED |
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| 38 | "STR R0, [R1]\n" |
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| 39 | // End LED Test |
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| 40 | */ |
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| 41 | "LDR R1, =0xC0410000\n" |
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| 42 | "MOV R0, #0\n" |
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| 43 | "STR R0, [R1]\n" |
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| 44 | "MOV R1, #0x78\n" |
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| 45 | "MCR p15, 0, R1,c1,c0\n" |
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| 46 | "MOV R1, #0\n" |
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| 47 | "MCR p15, 0, R1,c7,c10, 4\n" |
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| 48 | "MCR p15, 0, R1,c7,c5\n" |
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| 49 | "MCR p15, 0, R1,c7,c6\n" |
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| 50 | "MOV R0, #0x3D\n" |
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| 51 | "MCR p15, 0, R0,c6,c0\n" |
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| 52 | "MOV R0, #0xC000002F\n" |
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| 53 | "MCR p15, 0, R0,c6,c1\n" |
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| 54 | "MOV R0, #0x31\n" |
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| 55 | "MCR p15, 0, R0,c6,c2\n" |
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| 56 | "LDR R0, =0x10000031\n" |
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| 57 | "MCR p15, 0, R0,c6,c3\n" |
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| 58 | "MOV R0, #0x40000017\n" |
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| 59 | "MCR p15, 0, R0,c6,c4\n" |
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| 60 | "LDR R0, =0xFFC0002B\n" |
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| 61 | "MCR p15, 0, R0,c6,c5\n" |
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| 62 | "MOV R0, #0x34\n" |
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| 63 | "MCR p15, 0, R0,c2,c0\n" |
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| 64 | "MOV R0, #0x34\n" |
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| 65 | "MCR p15, 0, R0,c2,c0, 1\n" |
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| 66 | "MOV R0, #0x34\n" |
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| 67 | "MCR p15, 0, R0,c3,c0\n" |
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| 68 | "LDR R0, =0x3333330\n" |
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| 69 | "MCR p15, 0, R0,c5,c0, 2\n" |
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| 70 | "LDR R0, =0x3333330\n" |
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| 71 | "MCR p15, 0, R0,c5,c0, 3\n" |
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| 72 | "MRC p15, 0, R0,c1,c0\n" |
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| 73 | "ORR R0, R0, #0x1000\n" |
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| 74 | "ORR R0, R0, #4\n" |
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| 75 | "ORR R0, R0, #1\n" |
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| 76 | "MCR p15, 0, R0,c1,c0\n" |
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| 77 | "MOV R1, #0x40000006\n" |
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| 78 | "MCR p15, 0, R1,c9,c1\n" |
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| 79 | "MOV R1, #6\n" |
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| 80 | "MCR p15, 0, R1,c9,c1, 1\n" |
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| 81 | "MRC p15, 0, R1,c1,c0\n" |
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| 82 | "ORR R1, R1, #0x50000\n" |
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| 83 | "MCR p15, 0, R1,c1,c0\n" |
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| 84 | "LDR R2, =0xC0200000\n" |
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| 85 | "MOV R1, #1\n" |
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| 86 | "STR R1, [R2,#0x10C]\n" |
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| 87 | "MOV R1, #0xFF\n" |
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| 88 | "STR R1, [R2,#0xC]\n" |
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| 89 | "STR R1, [R2,#0x1C]\n" |
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| 90 | "STR R1, [R2,#0x2C]\n" |
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| 91 | "STR R1, [R2,#0x3C]\n" |
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| 92 | "STR R1, [R2,#0x4C]\n" |
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| 93 | "STR R1, [R2,#0x5C]\n" |
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| 94 | "STR R1, [R2,#0x6C]\n" |
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| 95 | "STR R1, [R2,#0x7C]\n" |
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| 96 | "STR R1, [R2,#0x8C]\n" |
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| 97 | "STR R1, [R2,#0x9C]\n" |
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| 98 | "STR R1, [R2,#0xAC]\n" |
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| 99 | "STR R1, [R2,#0xBC]\n" |
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| 100 | "STR R1, [R2,#0xCC]\n" |
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| 101 | "STR R1, [R2,#0xDC]\n" |
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| 102 | "STR R1, [R2,#0xEC]\n" |
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| 103 | "STR R1, [R2,#0xFC]\n" |
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| 104 | "LDR R1, =0xC0400008\n" |
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| 105 | "LDR R2, =0x430005\n" |
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| 106 | "STR R2, [R1]\n" |
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| 107 | "MOV R1, #1\n" |
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| 108 | "LDR R2, =0xC0243100\n" |
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| 109 | "STR R2, [R1]\n" |
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| 110 | "LDR R2, =0xC0242010\n" |
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| 111 | "LDR R1, [R2]\n" |
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| 112 | "ORR R1, R1, #1\n" |
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| 113 | "STR R1, [R2]\n" |
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| 114 | "LDR R0, =0xFFEE6708 \n" |
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| 115 | "LDR R1, =0x1900\n" |
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| 116 | "LDR R3, =0xAB04\n" |
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| 117 | "loc_FFC0013C:\n" |
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| 118 | "CMP R1, R3\n" |
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| 119 | "LDRCC R2, [R0],#4\n" |
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| 120 | "STRCC R2, [R1],#4\n" |
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| 121 | "BCC loc_FFC0013C\n" |
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| 122 | "LDR R1, =0x129140\n" |
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| 123 | "MOV R2, #0\n" |
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| 124 | "loc_FFC00154:\n" |
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| 125 | "CMP R3, R1\n" |
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| 126 | "STRCC R2, [R3],#4\n" |
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| 127 | "BCC loc_FFC00154\n" |
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| 128 | "B sub_FFC00358_my\n" //---------> |
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| 129 | ); |
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| 130 | }; |
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| 131 | |
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| 132 | |
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| 133 | void __attribute__((naked,noinline)) sub_FFC00358_my() { |
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| 134 | *(int*)0x1934=(int)taskHook; //http://chdk.setepontos.com/index.php/topic,4194.0.html |
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| 135 | *(int*)0x1938=(int)taskHook; |
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| 136 | |
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| 137 | // Replacement of sub_FFC00358 for correct power-on (power button=shoot mode, play button=play mode). |
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| 138 | *(int*)(0x20F4)= (*(int*)0xC022005C) & 1 ? 0x4000000 : 0x2000000; // 0x20f4=FFC42F34 |
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| 139 | |
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| 140 | asm volatile ( |
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| 141 | "LDR R0, =0xFFC003D0\n" |
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| 142 | "MOV R1, #0\n" |
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| 143 | "LDR R3, =0xFFC00408\n" |
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| 144 | "loc_FFC00364:\n" |
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| 145 | "CMP R0, R3\n" |
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| 146 | "LDRCC R2, [R0],#4\n" |
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| 147 | "STRCC R2, [R1],#4\n" |
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| 148 | "BCC loc_FFC00364\n" |
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| 149 | "LDR R0, =0xFFC00408\n" |
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| 150 | "MOV R1, #0x4B0\n" |
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| 151 | "LDR R3, =0xFFC0061C\n" |
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| 152 | "loc_FFC00380:\n" |
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| 153 | "CMP R0, R3\n" |
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| 154 | "LDRCC R2, [R0],#4\n" |
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| 155 | "STRCC R2, [R1],#4\n" |
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| 156 | "BCC loc_FFC00380\n" |
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| 157 | "MOV R0, #0xD2\n" |
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| 158 | "MSR CPSR_cxsf, R0\n" |
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| 159 | "MOV SP, #0x1000\n" |
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| 160 | "MOV R0, #0xD3\n" |
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| 161 | "MSR CPSR_cxsf, R0\n" |
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| 162 | "MOV SP, #0x1000\n" |
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| 163 | "LDR R0, =0x6C4\n" |
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| 164 | "LDR R2, =0xEEEEEEEE\n" |
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| 165 | "MOV R3, #0x1000\n" |
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| 166 | "loc_FFC003B4:\n" |
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| 167 | "CMP R0, R3\n" |
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| 168 | "STRCC R2, [R0],#4\n" |
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| 169 | "BCC loc_FFC003B4\n" |
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| 170 | "BL sub_FFC0119C_my\n" //--------> |
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| 171 | ); |
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| 172 | } |
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| 173 | |
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| 174 | void __attribute__((naked,noinline)) sub_FFC0119C_my() { |
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| 175 | asm volatile ( |
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| 176 | "STR LR, [SP,#-4]!\n" |
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| 177 | "SUB SP, SP, #0x74\n" |
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| 178 | "MOV R0, SP\n" |
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| 179 | "MOV R1, #0x74\n" |
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| 180 | "BL sub_FFE7E2BC\n" |
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| 181 | "MOV R0, #0x53000\n" |
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| 182 | "STR R0, [SP,#4]\n" |
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| 183 | // "LDR R0, =0x129140\n" // - |
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| 184 | "LDR R0, =new_sa\n" // + |
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| 185 | "LDR R0, [R0]\n" // + |
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| 186 | "LDR R2, =0x279C00\n" |
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| 187 | "LDR R1, =0x2724A8\n" |
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| 188 | "STR R0, [SP,#8]\n" |
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| 189 | "SUB R0, R1, R0\n" |
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| 190 | "ADD R3, SP, #0xC\n" |
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| 191 | "STR R2, [SP]\n" |
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| 192 | "STMIA R3, {R0-R2}\n" |
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| 193 | "MOV R0, #0x22\n" |
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| 194 | "STR R0, [SP,#0x18]\n" |
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| 195 | "MOV R0, #0x68\n" |
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| 196 | "STR R0, [SP,#0x1C]\n" |
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| 197 | "LDR R0, =0x19B\n" |
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| 198 | "LDR R1, =sub_FFC05E5C_my\n" //---------> |
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| 199 | "B sub_FFC011F0\n" // continue in firmware |
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| 200 | ); |
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| 201 | } |
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| 202 | |
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| 203 | |
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| 204 | void __attribute__((naked,noinline)) sub_FFC05E5C_my() { |
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| 205 | asm volatile ( |
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| 206 | "STMFD SP!, {R4,LR}\n" |
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| 207 | "BL sub_FFC00B24\n" |
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| 208 | "BL sub_FFC0A8D0\n" // dmsetup |
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| 209 | "CMP R0, #0\n" |
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| 210 | "LDRLT R0, =0xFFC05F70\n" |
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| 211 | "BLLT sub_FFC05F50\n" // err_init_task |
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| 212 | "BL sub_FFC05A98\n" |
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| 213 | "CMP R0, #0\n" |
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| 214 | "LDRLT R0, =0xFFC05F78\n" |
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| 215 | "BLLT sub_FFC05F50\n" |
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| 216 | "LDR R0, =0xFFC05F88\n" |
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| 217 | "BL sub_FFC05B80\n" |
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| 218 | "CMP R0, #0\n" |
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| 219 | "LDRLT R0, =0xFFC05F90\n" |
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| 220 | "BLLT sub_FFC05F50\n" |
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| 221 | "LDR R0, =0xFFC05F88\n" |
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| 222 | "BL sub_FFC03BF4\n" |
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| 223 | "CMP R0, #0\n" |
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| 224 | "LDRLT R0, =0xFFC05FA4\n" |
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| 225 | "BLLT sub_FFC05F50\n" |
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| 226 | "BL sub_FFC0A2C8\n" |
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| 227 | "CMP R0, #0\n" |
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| 228 | "LDRLT R0, =0xFFC05FB0\n" |
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| 229 | "BLLT sub_FFC05F50\n" |
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| 230 | "BL sub_FFC01680\n" |
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| 231 | "CMP R0, #0\n" |
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| 232 | "LDRLT R0, =0xFFC05FBC\n" |
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| 233 | "BLLT sub_FFC05F50\n" |
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| 234 | "LDMFD SP!, {R4,LR}\n" |
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| 235 | "B taskcreate_Startup_my\n" //--------> |
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| 236 | ); |
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| 237 | }; |
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| 238 | |
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| 239 | // ROM:0xFFC10654 |
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| 240 | void __attribute__((naked,noinline)) taskcreate_Startup_my() { |
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| 241 | asm volatile ( |
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| 242 | "STMFD SP!, {R3,LR}\n" |
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| 243 | // "BL j_nullsub_192\n" |
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| 244 | "BL sub_FFC2ABA8\n" |
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| 245 | "CMP R0, #0\n" |
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| 246 | "BNE loc_FFC10690\n" |
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| 247 | "BL sub_FFC250C0\n" |
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| 248 | "CMP R0, #0\n" |
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| 249 | "BEQ loc_FFC10690\n" |
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| 250 | "BL sub_FFC238CC\n" |
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| 251 | "CMP R0, #0\n" |
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| 252 | "BNE loc_FFC10690\n" |
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| 253 | "LDR R1, =0xC0220000\n" |
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| 254 | "MOV R0, #0x44\n" |
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| 255 | "STR R0, [R1,#0x20]\n" |
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| 256 | "loc_FFC1068C:\n" |
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| 257 | "B loc_FFC1068C\n" |
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| 258 | "loc_FFC10690:\n" |
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| 259 | // "BL sub_FFC238D8\n" // removed for correct power-on on 'on/off' button. |
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| 260 | // "BL j_nullsub_193\n" |
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| 261 | "BL sub_FFC28FD8\n" |
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| 262 | "LDR R1, =0x2CE000\n" |
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| 263 | "MOV R0, #0\n" |
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| 264 | "BL sub_FFC29220\n" |
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| 265 | "BL sub_FFC291CC\n" |
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| 266 | "MOV R3, #0\n" |
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| 267 | "STR R3, [SP]\n" |
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| 268 | "LDR R3, =task_Startup_my\n" //--------> |
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| 269 | "B sub_FFC106B8\n" // Continue in firmware |
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| 270 | ); |
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| 271 | } |
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| 272 | // ROM:0xFFC105F8 |
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| 273 | void __attribute__((naked,noinline)) task_Startup_my() { |
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| 274 | asm volatile ( |
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| 275 | "STMFD SP!, {R4,LR}\n" |
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| 276 | "BL sub_FFC06278\n" |
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| 277 | "BL sub_FFC249D0\n" |
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| 278 | "BL sub_FFC2326C\n" |
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| 279 | // "BL j_nullsub_196\n" |
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| 280 | "BL sub_FFC2ADD4\n" |
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| 281 | // "BL sub_FFC2AC7C\n" // - start diskboot.bin |
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| 282 | "BL sub_FFC2AF70\n" |
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| 283 | "BL sub_FFC2AE04\n" |
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| 284 | "BL sub_FFC28470\n" |
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| 285 | "BL sub_FFC2AF74\n" |
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| 286 | "BL CreateTask_spytask\n" // + |
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| 287 | // "BL sub_FFC237C0\n" // original taskcreate_PhySw |
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| 288 | "BL taskcreate_PhySw_my\n" // + ----------> |
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| 289 | "B sub_FFC10628\n" // continue in firmware |
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| 290 | ); |
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| 291 | } |
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| 292 | |
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| 293 | // ROM:FFC237C0 taskcreate_PhySw |
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| 294 | void __attribute__((naked,noinline)) taskcreate_PhySw_my() { |
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| 295 | asm volatile( |
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| 296 | "STMFD SP!, {R3-R5,LR}\n" |
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| 297 | "LDR R4, =0x1BE4\n" |
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| 298 | "LDR R0, [R4,#0x10]\n" |
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| 299 | "CMP R0, #0\n" |
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| 300 | "BNE sub_FFC237F4\n" // continue in firmware |
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| 301 | "MOV R3, #0\n" |
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| 302 | "STR R3, [SP]\n" |
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| 303 | "LDR R3, =mykbd_task\n" // Changed |
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| 304 | // "MOV R2, #0x800\n" |
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| 305 | "MOV R2, #0x2000\n" // + stack size for new task_PhySw so we don't have to do stack switch |
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| 306 | "B sub_FFC237E4\n" // Continue code |
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| 307 | ); |
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| 308 | } |
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| 309 | /*******************************************************************/ |
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| 310 | |
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| 311 | // ROM:FFC704B4 task_InitFileModules |
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| 312 | void __attribute__((naked,noinline)) init_file_modules_task() { |
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| 313 | asm volatile( |
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| 314 | "STMFD SP!, {R4-R6,LR}\n" |
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| 315 | "BL sub_FFC69D70\n" |
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| 316 | "LDR R5, =0x5006\n" |
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| 317 | "MOVS R4, R0\n" |
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| 318 | "MOVNE R1, #0\n" |
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| 319 | "MOVNE R0, R5\n" |
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| 320 | "BLNE sub_FFC6C5F8\n" |
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| 321 | "BL sub_FFC69D9C_my\n" //-------------> |
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| 322 | "BL core_spytask_can_start\n" // + set "it's safe to start" flag for spytask |
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| 323 | "B sub_FFC704D4\n" // continue in firmware |
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| 324 | ); |
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| 325 | } |
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| 326 | |
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| 327 | void __attribute__((naked,noinline)) sub_FFC69D9C_my() { |
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| 328 | asm volatile( |
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| 329 | "STMFD SP!, {R4,LR}\n" |
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| 330 | "MOV R0, #3\n" |
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| 331 | "BL sub_FFC50E90_my\n" //----------> |
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| 332 | "B sub_FFC69DA8\n" // continue in firmware |
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| 333 | ); |
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| 334 | } |
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| 335 | |
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| 336 | |
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| 337 | void __attribute__((naked,noinline)) sub_FFC50E90_my() { |
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| 338 | asm volatile( |
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| 339 | "STMFD SP!, {R4-R8,LR}\n" |
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| 340 | "MOV R8, R0\n" |
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| 341 | "BL sub_FFC50E10\n" |
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| 342 | "LDR R1, =0x322B0\n" |
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| 343 | "MOV R6, R0\n" |
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| 344 | "ADD R4, R1, R0,LSL#7\n" |
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| 345 | "LDR R0, [R4,#0x6C]\n" |
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| 346 | "CMP R0, #4\n" |
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| 347 | "LDREQ R1, =0x817\n" |
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| 348 | "LDREQ R0, =0xFFC50950\n" |
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| 349 | "BLEQ sub_FFC0F680\n" |
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| 350 | "MOV R1, R8\n" |
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| 351 | "MOV R0, R6\n" |
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| 352 | "BL sub_FFC506C8\n" |
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| 353 | "LDR R0, [R4,#0x38]\n" |
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| 354 | "BL sub_FFC51530\n" |
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| 355 | "CMP R0, #0\n" |
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| 356 | "STREQ R0, [R4,#0x6C]\n" |
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| 357 | "MOV R0, R6\n" |
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| 358 | "BL sub_FFC50758\n" |
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| 359 | "MOV R0, R6\n" |
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| 360 | "BL sub_FFC50AB8_my\n" //---------> |
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| 361 | "B sub_FFC50EE8\n" // continue in firmware |
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| 362 | ); |
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| 363 | } |
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| 364 | |
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| 365 | void __attribute__((naked,noinline)) sub_FFC50AB8_my() { |
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| 366 | asm volatile( |
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| 367 | "STMFD SP!, {R4-R6,LR}\n" |
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| 368 | "MOV R5, R0\n" |
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| 369 | "LDR R0, =0x322B0\n" |
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| 370 | "ADD R4, R0, R5,LSL#7\n" |
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| 371 | "LDR R0, [R4,#0x6C]\n" |
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| 372 | "TST R0, #2\n" |
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| 373 | "MOVNE R0, #1\n" |
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| 374 | "LDMNEFD SP!, {R4-R6,PC}\n" |
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| 375 | "LDR R0, [R4,#0x38]\n" |
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| 376 | "MOV R1, R5\n" |
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| 377 | "BL sub_FFC507D8_my\n" //---------> |
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| 378 | "B sub_FFC50AE4\n" // continue in firmware |
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| 379 | ); |
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| 380 | } |
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| 381 | |
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| 382 | void __attribute__((naked,noinline)) sub_FFC507D8_my() { |
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| 383 | asm volatile( |
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| 384 | "STMFD SP!, {R4-R10,LR}\n" |
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| 385 | "MOV R9, R0\n" |
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| 386 | "LDR R0, =0x322B0\n" |
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| 387 | "MOV R8, #0\n" |
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| 388 | "ADD R5, R0, R1,LSL#7\n" |
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| 389 | "LDR R0, [R5,#0x3C]\n" |
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| 390 | "MOV R7, #0\n" |
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| 391 | "CMP R0, #7\n" |
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| 392 | "MOV R6, #0\n" |
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| 393 | "ADDLS PC, PC, R0,LSL#2\n" |
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| 394 | "B loc_FFC50930\n" |
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| 395 | "loc_FFC50804:\n" |
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| 396 | "B loc_FFC5083C\n" |
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| 397 | "loc_FFC50808:\n" |
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| 398 | "B loc_FFC50824\n" |
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| 399 | "loc_FFC5080C:\n" |
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| 400 | "B loc_FFC50824\n" |
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| 401 | "loc_FFC50810:\n" |
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| 402 | "B loc_FFC50824\n" |
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| 403 | "loc_FFC50814:\n" |
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| 404 | "B loc_FFC50824\n" |
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| 405 | "loc_FFC50818:\n" |
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| 406 | "B loc_FFC50928\n" |
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| 407 | "loc_FFC5081C:\n" |
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| 408 | "B loc_FFC50824\n" |
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| 409 | "loc_FFC50820:\n" |
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| 410 | "B loc_FFC50824\n" |
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| 411 | "loc_FFC50824:\n" |
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| 412 | "MOV R2, #0\n" |
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| 413 | "MOV R1, #0x200\n" |
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| 414 | "MOV R0, #2\n" |
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| 415 | "BL sub_FFC63F9C\n" |
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| 416 | "MOVS R4, R0\n" |
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| 417 | "BNE loc_FFC50844\n" |
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| 418 | "loc_FFC5083C:\n" |
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| 419 | "MOV R0, #0\n" |
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| 420 | "LDMFD SP!, {R4-R10,PC}\n" |
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| 421 | "loc_FFC50844:\n" |
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| 422 | "LDR R12, [R5,#0x50]\n" |
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| 423 | "MOV R3, R4\n" |
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| 424 | "MOV R2, #1\n" |
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| 425 | "MOV R1, #0\n" |
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| 426 | "MOV R0, R9\n" |
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| 427 | "BLX R12\n" |
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| 428 | "CMP R0, #1\n" |
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| 429 | "BNE loc_FFC50870\n" |
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| 430 | "MOV R0, #2\n" |
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| 431 | "BL sub_FFC640E8\n" |
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| 432 | "B loc_FFC5083C\n" |
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| 433 | "loc_FFC50870:\n" |
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| 434 | "LDR R1, [R5,#0x64]\n" |
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| 435 | "MOV R0, R9\n" |
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| 436 | "BLX R1\n" |
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| 437 | |
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| 438 | "MOV R1, R4\n" // + pointer to MBR in R1 |
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| 439 | "BL mbr_read_dryos\n" // + total sectors count in R0 before and after call |
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| 440 | |
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| 441 | // Start of DataGhost's FAT32 autodetection code |
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| 442 | // Policy: If there is a partition which has type W95 FAT32, use the first one of those for image storage |
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| 443 | // According to the code below, we can use R1, R2, R3 and R12. |
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| 444 | // LR wasn't really used anywhere but for storing a part of the partition signature. This is the only thing |
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| 445 | // that won't work with an offset, but since we can load from LR+offset into LR, we can use this to do that :) |
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| 446 | "MOV R12, R4\n" // Copy the MBR start address so we have something to work with |
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| 447 | "MOV LR, R4\n" // Save old offset for MBR signature |
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| 448 | "MOV R1, #1\n" // Note the current partition number |
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| 449 | "B dg_sd_fat32_enter\n" // We actually need to check the first partition as well, no increments yet! |
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| 450 | "dg_sd_fat32:\n" |
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| 451 | "CMP R1, #4\n" // Did we already see the 4th partition? |
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| 452 | "BEQ dg_sd_fat32_end\n" // Yes, break. We didn't find anything, so don't change anything. |
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| 453 | "ADD R12, R12, #0x10\n" // Second partition |
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| 454 | "ADD R1, R1, #1\n" // Second partition for the loop |
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| 455 | "dg_sd_fat32_enter:\n" |
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| 456 | "LDRB R2, [R12, #0x1BE]\n" // Partition status |
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| 457 | "LDRB R3, [R12, #0x1C2]\n" // Partition type (FAT32 = 0xB) |
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| 458 | "CMP R3, #0xB\n" // Is this a FAT32 partition? |
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| 459 | "CMPNE R3, #0xC\n" // Not 0xB, is it 0xC (FAT32 LBA) then? |
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| 460 | "BNE dg_sd_fat32\n" // No, it isn't. Loop again. |
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| 461 | "CMP R2, #0x00\n" // It is, check the validity of the partition type |
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| 462 | "CMPNE R2, #0x80\n" |
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| 463 | "BNE dg_sd_fat32\n" // Invalid, go to next partition |
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| 464 | // This partition is valid, it's the first one, bingo! |
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| 465 | "MOV R4, R12\n" // Move the new MBR offset for the partition detection. |
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| 466 | |
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| 467 | "dg_sd_fat32_end:\n" |
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| 468 | // End of DataGhost's FAT32 autodetection code |
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| 469 | |
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| 470 | |
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| 471 | "LDRB R1, [R4,#0x1C9]\n" |
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| 472 | "LDRB R3, [R4,#0x1C8]\n" |
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| 473 | "LDRB R12, [R4,#0x1CC]\n" |
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| 474 | "MOV R1, R1,LSL#24\n" |
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| 475 | "ORR R1, R1, R3,LSL#16\n" |
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| 476 | "LDRB R3, [R4,#0x1C7]\n" |
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| 477 | "LDRB R2, [R4,#0x1BE]\n" |
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| 478 | // "LDRB LR, [R4,#0x1FF]\n" // - |
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| 479 | "ORR R1, R1, R3,LSL#8\n" |
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| 480 | "LDRB R3, [R4,#0x1C6]\n" |
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| 481 | "CMP R2, #0\n" |
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| 482 | "CMPNE R2, #0x80\n" |
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| 483 | "ORR R1, R1, R3\n" |
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| 484 | "LDRB R3, [R4,#0x1CD]\n" |
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| 485 | "MOV R3, R3,LSL#24\n" |
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| 486 | "ORR R3, R3, R12,LSL#16\n" |
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| 487 | "LDRB R12, [R4,#0x1CB]\n" |
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| 488 | "ORR R3, R3, R12,LSL#8\n" |
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| 489 | "LDRB R12, [R4,#0x1CA]\n" |
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| 490 | "ORR R3, R3, R12\n" |
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| 491 | // "LDRB R12, [R4,#0x1FE]\n" // - |
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| 492 | "LDRB R12, [LR,#0x1FE]\n" // + First MBR signature byte (0x55), LR is original offset. |
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| 493 | "LDRB LR, [LR,#0x1FF]\n" // + Last MBR signature byte (0xAA), LR is original offset. |
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| 494 | "BNE loc_FFC508FC\n" |
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| 495 | "CMP R0, R1\n" |
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| 496 | "BCC loc_FFC508FC\n" |
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| 497 | "ADD R2, R1, R3\n" |
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| 498 | "CMP R2, R0\n" |
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| 499 | "CMPLS R12, #0x55\n" |
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| 500 | "CMPEQ LR, #0xAA\n" |
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| 501 | "MOVEQ R7, R1\n" |
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| 502 | "MOVEQ R6, R3\n" |
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| 503 | "MOVEQ R4, #1\n" |
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| 504 | "BEQ loc_FFC50900\n" |
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| 505 | "loc_FFC508FC:\n" |
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| 506 | "MOV R4, R8\n" |
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| 507 | "loc_FFC50900:\n" |
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| 508 | "MOV R0, #2\n" |
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| 509 | "BL sub_FFC640E8\n" |
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| 510 | "CMP R4, #0\n" |
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| 511 | "BNE loc_FFC5093C\n" |
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| 512 | "LDR R1, [R5,#0x64]\n" |
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| 513 | "MOV R7, #0\n" |
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| 514 | "MOV R0, R9\n" |
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| 515 | "BLX R1\n" |
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| 516 | "MOV R6, R0\n" |
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| 517 | "B loc_FFC5093C\n" |
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| 518 | "loc_FFC50928:\n" |
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| 519 | "MOV R6, #0x40\n" |
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| 520 | "B loc_FFC5093C\n" |
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| 521 | "loc_FFC50930:\n" |
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| 522 | "LDR R1, =0x572\n" |
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| 523 | "LDR R0, =0xFFC50950\n" |
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| 524 | "BL sub_FFC0F680\n" |
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| 525 | "loc_FFC5093C:\n" |
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| 526 | "STR R7, [R5,#0x44]!\n" |
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| 527 | "STMIB R5, {R6,R8}\n" |
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| 528 | "MOV R0, #1\n" |
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| 529 | "LDMFD SP!, {R4-R10,PC}\n" |
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| 530 | ); |
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| 531 | } |
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